Search - fifo verilog

[SourceCode] 采用格雷码的FIFO控制模块（verilog）

Description: 异步FIFO常用于存储、缓冲在两个异步时钟之间的数据传输。在异步电路中，由于时钟之间周期和相位完全独立，因而数据的丢失概率不为零。如何设计一个高可靠性、高速的异步FIFO电路便成为一个难点。本例采用格雷码方式，用verilog语言实现了异步FIFO控制，大大降低误码率，提高了可靠性。
Platform: | Size: 5440 | Author: hangman_102@126.com | Hits:

[Other] verilog_fifo

Description: verilog fifo
Platform: | Size: 4096 | Author: 王新 | Hits:

[VHDL-FPGA-Verilog] 9.16fifoasi

Description: 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
Platform: | Size: 2761728 | Author: yjb_21cn | Hits:

[CSharp] OS课题设计

Description: 任务设计一个虚拟存储区和内存工作区，并使用下述算法计算访问命中率。（1）先进先出的算法（FIFO）（2）最近最少使用算法（LRU）（3）最佳淘汰算法（OPT）（4）最少访问页面算法（LFU）（5）最近最不经常使用算法（NUR）命中率=（1 – 页面失效次数）/页地址流长度-mission design a virtual memory storage area and the work area and to use the following algorithm to visit the hit rate. (1) FIFO algorithm (FIFO) (2) at least recently used algorithm (LRU) (3) eliminated the best algorithm (OPT) (4) at least visit pages algorithm (LFU) (5) most recently used algorithm (NUR) life China rate = (1-pages failure number)/page-length addre
Platform: | Size: 2048 | Author: 东方少秋 | Hits:

[OS Develop] 请求分页存储管理方式

Description: 课程实验,自己做的一个关于请求分布的程序, 采用先进先出算法(FIFO)和最近最久未使用算法(LRU)进行页面的置换-courses experiments done on the request of a distribution procedures, FIFO-algorithm (FIFO) and the most recent time on the use of algorithms (LRU) page replacement
Platform: | Size: 360448 | Author: 陈任全 | Hits:

[Other] fifo0

Description: systemverilog编写的fifo例子-SystemVerilog examples prepared by the fifo
Platform: | Size: 1024 | Author: 王晓波 | Hits:

[Communication-Mobile] async_fifo.v

Description: the verilog model of async_fifo.
Platform: | Size: 1024 | Author: nightyboy | Hits:

[Other] HowtosimulateIPCore

Description: IP核生成器生成 ip 后有两个文件对我们比较有用，假设生成了一个 asyn_fifo 的核，则 asyn_fifo.veo 给出了例化该核方式（或者在 Edit－>Language Template->COREGEN 中找到 verilog/VHDL 的例化方式）。asyn_fifo.v 是该核的行为模型，主要调用了 xilinx 行为模型库的模块，仿真时该文件也要加入工程。-IP core generator generate ip after two documents more useful to us. Formation of a hypothetical nuclear asyn_fifo, asyn_fifo.veo were given cases of the methods (or Edit-
Platform: | Size: 359424 | Author: 任学 | Hits:

[VHDL-FPGA-Verilog] simple_fifo

Description: verilog HDL原码一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Platform: | Size: 1024 | Author: zxz | Hits:

[Other] FIFO_Memory

Description: VHDL设计——FIFO存储器设计-VHDL design-- FIFO design
Platform: | Size: 7168 | Author: 钱伟康 | Hits:

[VHDL-FPGA-Verilog] verilogfifo

Description: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Platform: | Size: 1024 | Author: zzm | Hits:

[VHDL-FPGA-Verilog] xapp935

Description: ddr2 controller, verilog source code from xilinx
Platform: | Size: 347136 | Author: Hubert | Hits:

[VHDL-FPGA-Verilog] !061210[1].pdf

Description: 基于FPGA的异步FIFO的软硬件实现,通过VERILOG编程实现后下载到FPGA芯片-FPGA-based hardware and software asynchronous FIFO to achieve, through the Verilog programming downloaded to the FPGA chip after
Platform: | Size: 241664 | Author: youren | Hits:

[ARM-PowerPC-ColdFire-MIPS] FIFO_Buffer

Description: 同步及异步时序电路fifo源程序及其测试程序.rar - fifo源程序，erilog编写~具有较强的参考价值~ -Synchronous and asynchronous sequential circuits fifo source and test procedures. Rar- fifo source, erilog prepared ~ has a strong reference to the value of ~
Platform: | Size: 69632 | Author: 张勇奇 | Hits:

[VHDL-FPGA-Verilog] 4VerilogFIFO

Description: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 2048 | Author: shenyunfei | Hits:

[Other Embeded program] FIFO_synthesised

Description: verilog语言编写可综合FIFO。简单实用-Verilog languages can be integrated FIFO. Simple and practical
Platform: | Size: 3072 | Author: 苗苗 | Hits:

[VHDL-FPGA-Verilog] s_fifo

Description: 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench-Verilog language describes a synchronous fifo, including: Fifo using declared registers for storage and Fifo using (model of) standard memory chip for storage. In two ways, including Testbench
Platform: | Size: 2048 | Author: 彭帅 | Hits:

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